A typical metal-oxide-semiconductor (MOS) transistor 5 according to the prior art is shown in FIG. 1. Dielectric layer 20 is formed on a semiconductor 10 and a transistor gate structure 30 is formed on the dielectric layer 20. In a self-aligned dopant implantation process, the drain and source extension regions 40 are formed following the formation of the gate structure 30. These drain and source extension regions 40 can be n-type or p-type for NMOS or PMOS transistors respectively. Typically the drain and source extension regions 40 are more lightly doped than the source and drain regions 60 and are referred to as lightly doped drain (LDD) or moderately doped drain (MDD) extension regions depending on the relative doping concentration of the extension regions 40 with respect to the source and drain regions 60. Following the formation of the LDD or MDD regions 40, sidewall structures 50 are formed adjacent to the gate structure 30. The source and drain regions 60 are the formed by implanting dopant species into the semiconductor 10. The implanted dopant species used to form the source and drain regions 60 are self-aligned to the sidewall structures 50. Metal silicide 70 is then formed on both the source and drain 60 and on the gate structure 30 to reduce the resistance associated with these regions.
As described above, the LDD or MDD regions 40 are relatively lightly doped and therefore contribute parasitic resistance to the MOS transistor. Parasitic resistance reduces the performance of the MOs transistor by reducing the voltage that appears across the channel region. As the gate length of the MOS transistor is reduced the parasitic resistances associated with the LDD and MDD regions will become a large limitation in improving the performance of the transistor. There is therefore a need for a MOS transistor with reduced parasitic resistances. The instant invention addresses this need.